RAMs can be among the top consumers of dynamic power in some integrated circuit (IC) applications. The dynamic power consumption of an IC is a function of the power consumed when the circuit changes state and the power used to charge the load capacitance when the circuit changes logic states. Thus, a reduction in switching activity can provide a corresponding reduction in dynamic power consumption.
Optimizing dynamic power consumption often employs gating the clock signal to seldom used parts of an integrated circuit. Clock gating functions on the assumption that for some number of clock cycles the clock-gated circuitry is not needed. However, gating the clock signal to a RAM may be ineffective. For RAMs, clock gating can be ineffective because the application logic accesses different parts of the RAM at different times.